As a method for writing information into a flash memory or an EEPROM as a non-volatile semiconductor memory device, such a method is widely used that channel hot electrons (CHEs) are generated in a channel region of a memory transistor and the generated channel hot electrons are injected into a charge storage or trapping layer of the memory transistor.
The writing method through the CHE injection may need to provide large current between a source and a drain of a selector transistor of such a memory device, resulting in large current dissipation.
As a further method for writing information into a memory cell without providing current flowing through such a channel region, such a writing method through avalanche injection is used that electrons or holes are generated by avalanche breakdown or band-to-band tunneling (BTBT) and the generated electrons or holes are injected into a charge storage or trapping layer of the memory transistor.
Similarly to the writing method through CHE injection, the writing method through avalanche injection performs a write operation by applying a voltage to a gate electrode and a source diffusion region of the memory transistor. However, the writing method through avalanche injection is different from the writing method through CHE injection in that the writing method through avalanche injection performs a write operation only by the use of substrate current.
A NOR-type memory cell formed of two transistors, i.e. a selector transistor and a memory transistor, is disclosed in Japanese Laid-open Patent Application Publication JP 2005-116970-A (patent document 1), for example.
In order to reduce current consumption in the two-transistor cell described above, it is desirable to employ such a writing method through avalanche injection. In this case, however, the selector transistor cannot control substrate current, and hence the selector transistor cannot be used to control enabling or disabling a write operation. Thus, a memory circuit of FIG. 2 in patent document 1 described above, which uses two-transistor cells for a NOR-type flash memory, has its memory transistors disposed on a side of a bit line and selects the memory transistor with the bit line and a word line.
However, coupling of the memory transistor to the bit line may provide variable parasitic capacitance formed by the memory transistor depending on its different written state, which may provide an unstable read operation. Thus, for providing a stable read operation, it is desirable to dispose the selector transistors on the side of the bit line and dispose the memory transistors on the side of the source line.
On the other hand, a memory circuit which couples selector transistors of two-transistor cells to a bit line and employs the writing method through CHE injection is disclosed in Japanese Laid-open Patent Application Publication JP 2005-122772-A (patent document 2). This memory circuit has a configuration such that a plurality of memory transistors which are coupled to a shared word line have respective source regions coupled to a shared source line.
If this memory circuit employs the writing method through avalanche injection to apply a voltage between the word line and the source line, the memory transistors are caused to be simultaneously in write enable states so that any of the memory transistors cannot be selected.
In addition, Japanese Laid-open Patent Application Publication JP HEI 11-177068-A (patent document 3), FIG. 10, discloses a memory circuit which employs the writing method through CHE injection. In this memory circuit, drain regions of selector transistors are coupled to a bit line, and source regions of memory transistors are coupled to a source line.
However, the memory circuit of patent document 3 described above provides no direct coupling between two-transistor cells and provides a source line and a bit line disposed for each column of the cells, so that many junctions are provided between the source and bit lines and the transistors. Thus, this memory circuit has a larger area of memory cells than that of each of the memory circuits of patent documents 1 and 2 described above.